This invention relates generally to semiconductor devices, and, more particularly, to triple-gate transistors and methods for their manufacture.
Multi-gate transistors have been developed for next-generation devices. Example multi-gate transistor designs include dual-gate and triple-gate transistors, as well as quad-gate transistors and “PI”-gate transistors. These devices overcome performance and process limitations of conventional planar transistor devices due to a reduction in gate length accompanied with scale down.
For example, the length of the gate structure is typically the smallest dimension of conventional planar MOS transistors in order to increase device density, improve performance (e.g., increase switching speed), and to reduce power consumption. However, current photolithographic and etching techniques generally limit the extent to which transistor dimensions can be reliably scaled. In addition, as the gate length is reduced, the transistor performance can be inhibited by short channel effects, which can lead to an increased drain induced barrier lowering (DIBL) and/or an increased off-state current due to the threshold voltage (Vt) roll-off.
Multi-gate transistors provide more control over a scaled channel by situating the gate around two or more sides of the channel silicon, wherein a shorter channel length can be achieved for the same gate dielectric thickness or similar channel lengths can be used with thicker gate dielectrics.
Typically, a silicon-on-insulator (SOI) wafer is provided for conventional multi-gate transistors. The SOI wafer includes a substrate with an overlying oxide insulator and a 20.0-50.0 nm thick semiconductor layer above the oxide. The upper silicon layer is etched away, leaving isolated islands or blocks of silicon, and a gate is formed around the silicon blocks, with the ends of the blocks being doped to form source/drains. Because the gate extends on more than one peripheral side of the channel, multi-gate designs can alleviate the short channel effects seen in scaled planar transistors. In practice, however, the conventional multi-gate approaches have suffered from cost and performance shortcomings, because SOI wafers are more expensive than ordinary silicon substrates and because the channel surface has been etched while carving the upper SOI silicon layer into islands or blocks.
In addition, conventional multi-gate transistors include shallow trench isolation (STI) structures formed in the neighborhood of the device. Conventional STI structures typically generate a compressive stress in the channel region of the transistor. This reduces the carrier mobility and degrades the device performance. A conventional solution to reduce the detrimental effect of the STI structures is to recess the STI structures on bulk, i.e., the STI structures are thinned below the surface of the substrate. Problems arise, however, since recessing the STI structures exposes the silicon substrate at the sidewall of the substrate. As a result of the insufficient gate wrap, device performance degrades, especially as the devices are scaled down.
Thus, there is a need to address these and other problems of the prior art and to provide an improved multi-gate transistor device and manufacturing techniques to avoid shortcomings of conventional planar or multi-gate transistors and provide devices built on silicon substrates with improved isolation and improved spacing for denser devices.